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Implementation of dynamically reconfigurable processor DAPDNA-2

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3 Author(s)
T. Sato ; IPFlex Inc., Tokyo, Japan ; H. Watanabe ; K. Shiba

Application requirements for high computation power are increasing and becoming difficult to meet. Computer architectures based on program counters have been used for a long time along with the technologies as FPGAs or ASICs, for the acceleration using parallel data processing. However, these technologies have become expensive and the turn around time is getting longer than before. In order to solve these problems, the authors developed the DAPDNA-2 as a high performance processor solution using dynamically reconfigurable technology, which, using parallel data processing, could provide more flexibility and higher computation power. The performance of DAPDNA-2 is close to that of ASICs and it is easy to achieve customer's application requirement in a short development period. The design has been implemented with Fujitsu 0.13 μm CMOS technology with about 12 million gates and a clock frequency of 166 MHz. Exceptional performance results have been seen in typical application compared to that of Intel's Pentium IV running at 3 GHz.

Published in:

2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT).

Date of Conference:

27-29 April 2005