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JPEG2000 encoder architecture design with fast EBCOT algorithm

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2 Author(s)
Tsung-Han Tsai ; Dept. of Electr. Eng., National Central Univ., Chung-Li, Taiwan ; Lian-Tsung Tsai

This paper presents an architecture design for JPEG2000 with a fast algorithm in EBCOT. The EBCOT algorithm takes advantages of resolution and SNR scalability together with a random access property, but its complexity also becomes the bottleneck of JPEG2000. In this paper, the authors proposed a fast algorithm that uses two speed-up methods for EBCOT context modeling. The gate counts of JPEG2000 design is about 105.9 K gate with TSMC 0.25 μm technology. It can encode 4.2 million pixels per second at 40 MHz.

Published in:

2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT).

Date of Conference:

27-29 April 2005