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A multilevel sensing and program verifying scheme for Bi-NAND flash memories

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4 Author(s)
Chiu-Chiao Chung ; Dept. of Electr. Eng., National Chung-Hsing Univ., Taichung, Taiwan ; Hongchin Lin ; You-Min Shen ; Yen-Tai Lin

A multi-level sensing and program verifying circuit is proposed for Bi-NAND type flash memories. The sensing circuit utilizes the advanced cross-coupled sense amplifier to achieve excellent immunity against mismatch effect, and reduce power consumption. The program-verifying scheme with dichotomous architecture simplifies the verifying circuit and speeds up verification process for multi-level cell arrays.

Published in:

VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT). 2005 IEEE VLSI-TSA International Symposium on

Date of Conference:

27-29 April 2005

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