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An improved methodology for system-level point-to-point communication architecture synthesis in SOC design

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3 Author(s)
Hao-Yueh Hsieh ; Dept. of Comput. Sci., National Tsing Hua Univ., Hsinchu, Taiwan ; Bo-Wei Chen ; Ting-Chi Wang

In this paper, we present a simple yet effective technique to improve an existing methodology for system-level point-to-point communication architecture synthesis in SOC design. The technique enables the existing methodology to simultaneously consider the chip area, communication energy, and wirelength to evaluate a candidate communication architecture under performance constraints. The improved methodology has been tested on two cases and the experimental results indicate that the average wirelength and communication energy could be reduced by up to 20.4% and 4%, respectively while the average chip area increases at most 3.1%.

Published in:

VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT). 2005 IEEE VLSI-TSA International Symposium on

Date of Conference:

27-29 April 2005