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Off-state current and performance analysis for double-gate CMOS with non-self-aligned back gate

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4 Author(s)
Keunwoo Kim ; IBM T. J. Watson Res. Center, Yorktown Heights, NY, USA ; Hanafi, H.I. ; Jin Cai ; Ching-Te Chuang

Numerical simulation-based study of double-gate (DG) field-effect transistors (FETs) leads to the possibly viable concept of extremely scaled but nonself-aligned DG CMOS. Predictions of off-state current, on-state current, and circuit performance, accounting for short-channel effects and energy-quantization effects, in 25-nm DG FETs suggest that moderate back-gate underlap does not severely undermine the superior performance and leakage current of nanoscale DG CMOS relative to those of bulk-Si CMOS. The reverse back-gate biasing scheme for leakage reduction in DG CMOS is shown to be much more efficient than the reverse body biasing scheme in bulk Si even with moderate back-gate underlap.

Published in:

Electron Devices, IEEE Transactions on  (Volume:52 ,  Issue: 9 )

Date of Publication:

Sept. 2005

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