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In this paper, a Flash memory structure with the floating-gate at the opposite side of conduction channel (refer as OSFG-Flash) is proposed and demonstrated by two-dimensional (2-D) simulation. With the decoupling of the read oxide and tunneling oxide, very thin read oxide can be used to suppress short channel effect while a thick back-tunneling oxide around 10 nm can be used to provide sufficient charge retention time. Excellent scalability of the memory cell is demonstrated through a 2-D simulator down to 50 nm.
Date of Publication: Sept. 2005