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A three-dimensional stacked fin-CMOS technology for high-density ULSI circuits

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5 Author(s)
Xusheng Wu ; Dept. of Electr. & Electron. Eng., Hong Kong Univ. of Sci. & Technol., Kowloon, China ; Chan, Philip C.H. ; Shengdong Zhang ; Chuguang Feng
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In this paper, a three-dimensional CMOS technology is proposed and implemented using stacked Fin-CMOS (SF-CMOS) architecture. The technology is based on a double layer silicon-on-insulator wafer formed by two oxygen implants to create two single-crystal silicon films with an oxide isolation layer in between. The proposed approach achieves a 50% area reduction and significant shortening of the wiring distance between active devices through vertical connection when compared with conventional planar CMOS technology. The SF-CMOS technology also inherits the scalability and two-dimensional processing compatibility of the FinFET structure. SF-CMOS devices and simple circuits were fabricated and characterized.

Published in:

Electron Devices, IEEE Transactions on  (Volume:52 ,  Issue: 9 )

Date of Publication:

Sept. 2005

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