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A new 4H-SiC normally off lateral channel vertical JFET with extremely low power losses: source inserted double-gate structure with a supplementary highly doped region

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4 Author(s)
Young Chul Choi ; Sch. of Electr. & Comput. Eng., Cornell Univ., Ithaca, NY, USA ; Ho-Young Cha ; L. F. Eastman ; M. G. Spencer

A novel silicon carbide (SiC) normally off lateral channel vertical junction field-effect transistor (LC-VJFET), namely a source-inserted double-gate structure with a supplementary highly doped region (SHDR), was proposed for achieving extremely low power losses in high-power switching applications. The proposed architecture was based on the combination of an additional source electrode inserted between two adjacent surface gate electrodes and a unique SHDR in the vertical channel region. Two-dimensional numerical simulations for the static and resistive switching characteristics were performed to analyze and optimize the SiC LC-VJFET structures for this purpose. Based on the simulation results, the excellent performance of the proposed structure was compared with optimized conventional structures with regard to total power losses. Finally, the proposed structure showed about a 20% reduction in on-state loss (Pon) compared to the conventional structures, due to the effective suppression of the JFET effect. Furthermore, the switching loss (Psw) of the proposed structure was found to be much lower than the results of the conventional structures, about a 75% ∼ 95% reduction, by significantly reducing both input capacitance (Ciss) and reverse transfer capacitance (Crss) of the device.

Published in:

IEEE Transactions on Electron Devices  (Volume:52 ,  Issue: 9 )