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This paper presents an automated methodology for calibrating the doping profile and accurately predicting substrate parasitics with boundary element solvers. The technique requires fabrication of only a few test structures and results in an accurate three-layered approximation of a heavily doped epitaxial silicon substrate. Using this approximation, the extracted substrate resistances are accurate to within 10% of measurements. The calibrated parasitic extractor results in good agreement between simulations and measurements for substrate noise coupling in fabricated test circuits.
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on (Volume:13 , Issue: 7 )
Date of Publication: July 2005