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Presilicon modeling: challenges in the late CMOS era

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1 Author(s)

IEEE Micro editor in chief Pradip Bose writes that in a future of "integrated microarchitectures," high-end, server-class microprocessor chips will begin to look like system-on-chip designs with multiple processor cores, special-purpose accelerators invoked on demand, and a scalable on-chip interconnection network, among other on-chip heterogeneous elements. The resulting presilicon modeling challenges in the setting of this late CMOS design era are quite mind-boggling.

Published in:

Micro, IEEE  (Volume:25 ,  Issue: 4 )

Date of Publication:

July-Aug. 2005

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