By Topic

Presilicon modeling: challenges in the late CMOS era

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)

IEEE Micro editor in chief Pradip Bose writes that in a future of "integrated microarchitectures," high-end, server-class microprocessor chips will begin to look like system-on-chip designs with multiple processor cores, special-purpose accelerators invoked on demand, and a scalable on-chip interconnection network, among other on-chip heterogeneous elements. The resulting presilicon modeling challenges in the setting of this late CMOS design era are quite mind-boggling.

Published in:

Micro, IEEE  (Volume:25 ,  Issue: 4 )