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Distributed data-retention power gating techniques for column and row co-controlled embedded SRAM

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3 Author(s)
Chung-Hsien Hua ; Dept. of Electron. Eng., National Chiao-Tung Univ., Hsin-Chu, Taiwan ; Tung-Shuan Cheng ; Wei Hwang

In this paper, multi-mode data-retention power gating (P.G.) techniques are presented for embedded memories. These data retention power gating techniques are applied to embedded SRAM with distributed column and row co-controlled capabilities. The SRAM array is divided into blocks. Each block has a dedicated data-retention power gating device. The data-retention power gating devices are controlled by signals from both row and column decoders. Only the selected block is powered-on. Multi-mode power gating structures proposed in this paper can provide 2× to 20× memory cell leakage reduction while maintaining good static noise margin. Simulation results show that for a 64-bit wordline, the active power reductions for 32-bit, 16-bit, and 8-bit blocks are 59%, 79%, and 94%, respectively. All the simulations and physical layout are implemented in TSMC CMOS technology.

Published in:

Memory Technology, Design, and Testing, 2005. MTDT 2005. 2005 IEEE International Workshop on

Date of Conference:

5-5 Aug. 2005

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