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A novel CMOS compatible embedded nonvolatile memory with zero process adder

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5 Author(s)
Breitwisch, M.J. ; IBM Res. Div., Yorktown Heights, NY, USA ; Lam, C.H. ; Johnson, J.B. ; Mittl, S.W.
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We demonstrate a CMOS compatible reprogrammable nonvolatile memory cell using a regular n-channel MOSFET with under-lapped source/drain diffusions that requires no extra processing steps in a standard 130nm CMOS logic technology. Experimental results indicate good endurance and retention characteristics. A strategy for optimizing programming efficiency is identified with the addition of one extra mask to introduce drain optimization implants.

Published in:

Memory Technology, Design, and Testing, 2005. MTDT 2005. 2005 IEEE International Workshop on

Date of Conference:

5-5 Aug. 2005