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The simulation of memory circuits has been a challenge for analog simulators due to the requirement of handling high capacity and providing SPICE-like accuracy at the same time. New hierarchical isomorphic simulation technology was developed enabling the accurate simulation of nearly unlimited memory designs without performance penalty. The main technology concept is the compression of memory and computation for isomorphic subcircuits, which eliminates the need for cutting down designs to fit them into conventional simulation tools. With the arrival of nanometer technology the analysis of parasitic effects has become critical in verifying design functionality, timings, and power. This requires simulation tools not only to handle very large memories but also to analyze the effect of hundreds of million of parasitic elements. Several postlayout simulation flows are discussed and state-of-the-art RC reduction technology is introduced.