By Topic

Design of on-line testing for SoC with IEEE P1500 compliant cores using reconfigurable hardware and scan shift

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Katoh, K. ; Graduate Sch. of Sci. & Technol., Chiba Univ., Japan ; Doumar, A. ; Ito, H.

In this paper, a new design for online testing of system on a chip (SoC) is presented. The proposed method is based on usage of the available IEEE P1500 architecture and a small embedded FPGA core. Our method has a little additional routing overhead of the SoC, which keeps its performance much higher than conventional approaches. The design of this method is easy and it does not make a burden on the system designer. The error latency has an order of only few minutes in worst case scenario. We present the hardware implementation of this method and evaluate its performances.

Published in:

On-Line Testing Symposium, 2005. IOLTS 2005. 11th IEEE International

Date of Conference:

6-8 July 2005