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Design methodology of a low power high speed CMOS ADC

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3 Author(s)
Neelam Maman ; Dept. of Electron. & Comput. Eng., Indian Inst. of Technol., Roorkee, India ; Jharia, B. ; Agarwal, R.P.

This paper presents the design of a very low-power and high-speed, with a 70-75 MS/s 8b, CMOS analog to digital converter (ADC). The design equations are solved to achieve the complete architecture of the ADC. The maximum sampling speed achieved is 75 MHz at an analog power supply of 2.5 V. Total power consumption at full speed is 24.8 mW. The ADC is implemented using 0.35 μm MOSIS BSIM3 model.

Published in:

India Annual Conference, 2004. Proceedings of the IEEE INDICON 2004. First

Date of Conference:

20-22 Dec. 2004