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HALO: an efficient global placement strategy for standard cells

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2 Author(s)
Yang, Y.-Y. ; Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Seoul, South Korea ; Chong-Min Kyung

A standard cell placement procedure that is based on an efficient global placement strategy, called HALO (hierarchical alternating liner ordering), is proposed. This method generates a global 2D placement of circuit modules by hierarchical application of linear ordering in an alternating direction. The HALO global placement procedure is followed by a detailed placement procedure which consists of row assignment, feed-through cell assignment and intrarow cell assignment steps. Experimental results on two benchmark circuits, primary1 and primary2, consisting of 752 and 2907 cells, have shown decreases of the half-perimeter routing lengths by 7% and 24%, respectively, compared with the best available results obtained so far. Total CPU time, including the subsequent detailed placement, was less than half that of previously published work

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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:11 ,  Issue: 8 )