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Predicting system-level area and delay for pipelined and nonpipelined designs

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3 Author(s)
R. Jain ; Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA ; A. C. Parker ; N. Park

The ability to predict area-delay characteristics of designs without actually implementing them is important in producing quality designs in a reasonable time. A mathematical model for predicting the area-delay tradeoff curve for pipelined and nonpipelined data paths, given a data flow graph and a choice of module styles, is proposed. The model has been validated against designs generated by pipelined and nonpipelined data-path synthesis programs

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:11 ,  Issue: 8 )