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A 0.168μm2/0.11μm2 highly scalable high performance embedded DRAM cell for 90/65-nm logic applications

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9 Author(s)
Wang, G. ; IBM Semicond. R&D Center, Hopewell Junction, NY, USA ; Parries, P. ; Khan, B. ; Liu, J.
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A high performance embedded DRAM cell has been developed in 90nm technology using a pass transistor with standard 2.2nm gate oxide and trench capacitor. This device offers 25% on-current improvement with 1.5V wordline boosted voltage, and reduces the cell size by 10%. Measured data retention of >200μs is ideal for 200+MHz random access cycle embedded DRAM macro with a concurrent refresh mode. The scalability of the cell to 0.11 μm2 in 65-nm node is also demonstrated.

Published in:

VLSI Technology, 2005. (VLSI-TSA-Tech). 2005 IEEE VLSI-TSA International Symposium on

Date of Conference:

25-27 April 2005