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A novel process-induced strained silicon (PSS) CMOS technology for high-performance applications

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11 Author(s)
C. H. Ko ; Taiwan Semicond. Manuf. Co., Ltd., Hsinchu, Taiwan ; C. H. Ge ; C. C. Huang ; C. Y. Fu
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We report an optimized process-induced strained silicon (PSS) technology for 90nm CMOS generation and beyond. Through the superposition of various PSS techniques, up to 20% performance enhancement is achieved for both N- and PMOS at channel length down to 45nm. The PSS technology exhibits excellent gate oxide breakdown characteristics, isolation characteristics and reliability. A novel spacer-PSS technology is also proposed for the first time and ∼7% enhancement in ring oscillator speed is observed.

Published in:

IEEE VLSI-TSA International Symposium on VLSI Technology, 2005. (VLSI-TSA-Tech).

Date of Conference:

25-27 April 2005