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This paper proposes a versatile memory-interface architecture that, through a mode switch, uses a two-dimensional array of DRAM banks for both general-purpose data storage and picture (or video) data storage. Additionally, in picture mode, the architecture supports both linear and block access of video pixel data. An efficient mapping scheme that maps video pixel data into the memory bank array to hide DRAM row activation latency is also proposed. The proposed memory-interface architecture is suitable for embedded memory in system-on-chip applications or for enhancement of commodity DRAM chips.
IEEE-NEWCAS Conference, 2005. The 3rd International
Date of Conference: 19-22 June 2005