Design and implementation of a reconfigurable architecture for (528, 518) Reed-Solomon codec IP

In this paper, an area-efficient Reed-Solomon (RS) codec IP with composite-field inverter is presented. For some specific applications such as flash memory controller using RS (528, 518) code over GF(2/sup 10/) to correct 4 errors, the RS decoder will stop receiving any new codeword until the on-going erroneous codeword to be corrected. It is that the circuit complexity can be reduced by sharing the registers and finite-field operation units. Moreover, the proposed hardware sharing architecture also includes the RS encoder. After implementing by 0.18/spl mu/m 1P6M standard cell slow library, the RS (528, 518) codec IP totally requires 2 finite-field multiplier, 1 composite-field inverter and 17(=4t+1) registers, where t is the number of correctable errors. In contrast with other architectures, at least 42% circuit complexity can be reduced in our proposal.