By Topic

Design and implementation of a reconfigurable architecture for (528, 518) Reed-Solomon codec IP

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Fuh-ke Chang ; Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan ; Wei-Chun Hsu ; Chien-Ching Lin ; Hsie-Chia Chang

In this paper, an area-efficient Reed-Solomon (RS) codec IP with composite-field inverter is presented. For some specific applications such as flash memory controller using RS (528, 518) code over GF(210) to correct 4 errors, the RS decoder will stop receiving any new codeword until the on-going erroneous codeword to be corrected. It is that the circuit complexity can be reduced by sharing the registers and finite-field operation units. Moreover, the proposed hardware sharing architecture also includes the RS encoder. After implementing by 0.18μm 1P6M standard cell slow library, the RS (528, 518) codec IP totally requires 2 finite-field multiplier, 1 composite-field inverter and 17(=4t+1) registers, where t is the number of correctable errors. In contrast with other architectures, at least 42% circuit complexity can be reduced in our proposal.

Published in:

The 3rd International IEEE-NEWCAS Conference, 2005.

Date of Conference:

19-22 June 2005