Design of current-mode digital-to-analog converter in hybrid architecture

This paper proposed a current-mode digital-to-analog converter with a high resolution, high speed, and small hardware overhead. This design takes advantage of the weighted-current-steering approach and the R-/spl beta/R-ladder approach. The weighted-current-steering approach is used to implement the seven bits in the most-significant-bit stage while the R-/spl beta/R-ladder approach that is modified form the R-/spl beta/R approach is used to implement the nine bits in the least-significant-bit stage. This converter was designed with a TSMC 0.18-/spl mu/m 1P6M CMOS process. The HSPICE simulation results show that this design achieves a 16-b resolution with DNL and INL less than 0.5 LSB and 0.7 LSB, respectively. At 3.3-V supply voltage and 200-MHz operating frequency, the power consumption is 232 mW.