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Design of current-mode digital-to-analog converter in hybrid architecture

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3 Author(s)
Chuen-Yau Chen ; Dept. of Electr. Eng., Nat. Yunlin Univ. of Sci. & Technol., Taiwan ; Chi-Jung Cheng ; Chien-Cheng Yu

This paper proposed a current-mode digital-to-analog converter with a high resolution, high speed, and small hardware overhead. This design takes advantage of the weighted-current-steering approach and the R-βR-ladder approach. The weighted-current-steering approach is used to implement the seven bits in the most-significant-bit stage while the R-βR-ladder approach that is modified form the R-βR approach is used to implement the nine bits in the least-significant-bit stage. This converter was designed with a TSMC 0.18-μm 1P6M CMOS process. The HSPICE simulation results show that this design achieves a 16-b resolution with DNL and INL less than 0.5 LSB and 0.7 LSB, respectively. At 3.3-V supply voltage and 200-MHz operating frequency, the power consumption is 232 mW.

Published in:

IEEE-NEWCAS Conference, 2005. The 3rd International

Date of Conference:

19-22 June 2005