By Topic

Power-constrained system-on-a-chip test scheduling using a genetic algorithm

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Harmanani, H.M. ; Dept. of Comput. Sci. & Math., Lebanese American Univ., Byblos, Lebanon ; Salamy, H.A.

This paper presents a new and an efficient approach for the test scheduling problem of core-based systems based on a genetic algorithm. The method minimizes the overall test application time of a SoC through efficient and compact test schedules. The problem is solved using a "sessionless" scheme that minimizes the number of idle test slots. The method can handle SoC test scheduling with and without power constraints. We present experimental results for various SoC examples that demonstrate the effectiveness of our method in short CPU time.

Published in:

IEEE-NEWCAS Conference, 2005. The 3rd International

Date of Conference:

19-22 June 2005