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Power-constrained system-on-a-chip test scheduling using a genetic algorithm

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2 Author(s)
H. M. Harmanani ; Dept. of Comput. Sci. & Math., Lebanese American Univ., Byblos, Lebanon ; H. A. Salamy

This paper presents a new and an efficient approach for the test scheduling problem of core-based systems based on a genetic algorithm. The method minimizes the overall test application time of a SoC through efficient and compact test schedules. The problem is solved using a "sessionless" scheme that minimizes the number of idle test slots. The method can handle SoC test scheduling with and without power constraints. We present experimental results for various SoC examples that demonstrate the effectiveness of our method in short CPU time.

Published in:

The 3rd International IEEE-NEWCAS Conference, 2005.

Date of Conference:

19-22 June 2005