A 6.25Gb/s pipelined half-rate decision feedback equalizer for high speed backplane data communications

A pipelined two post-tap half-rate decision feedback equalizer (HRDFE) is proposed. The circuit is composed of equalizing circuit and sampling circuit working at half rate clock, with cross-coupling output of interleaving sampler feedback to the input. A behavioral model of the HRDFE is built in MATLAB to prove the feasibility of the circuit. The design is verified by using 0.18/spl mu/m CMOS process in SPECTRE. Simulation results show eye opening increases at speed up to 6.25Gb/s with data transmitted over a 34" FR4 backplane. The total power consumption is 8.91 mW with a 1.8V supply.