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A novel discrete relaxation architecture

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2 Author(s)
J. Gu ; Dept. of Electr. & Comput. Eng., Calgary Univ., Alta., Canada ; W. Wang

The discrete relaxation algorithm (DRA) is a computational technique that enforces arc consistency (AC) in a constraint satisfaction problem (CSP). The original sequential AC-1 algorithm suffers from O(n3m3) time complexity, and even the optimal sequential AC-4 algorithm is O (n2m2) for an n-object and m-label DRA problem. Sample problem runs show that these algorithms are all too slow to meet the need for any useful, real-time CSP applications. A parallel DRA5 algorithm that reaches a lower bound of O(nm) (where the number of processors is polynomial in the problem size) is given. A fine-grained, massively parallel hardware computer architecture has been designed for the DRA5 algorithm. For practical problems, many orders of magnitude of efficiency improvement can be reached on such a hardware architecture

Published in:

IEEE Transactions on Pattern Analysis and Machine Intelligence  (Volume:14 ,  Issue: 8 )