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A major impediment to the continuation of Moore's Law in the years to come is the performance of interconnections in ICs at high frequencies. Microprocessors are using a greater portion of their clock cycle charging and discharging interconnections. Silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs) provide a fast track technology for the exploration of the effect of interconnections on high-speed computer design. Industry has pursued low-k dielectrics to decrease wire capacitance. Cu metallization has been used to reduce wire resistance which becomes important as the wire dimensions are scaled down. These are not the only issues for high-frequency interconnections. Some other high-frequency issues include coupling, transmission line propagation, skin effects, and dielectric and substrate loss. These phenomena cause signal attenuation, noise, and dispersion in addition to delay. In the limit of zero device delay, interconnection delay will remain in addition to these problems. Wire shortening has been possible using more layers of interconnections, but this approach may be reaching its limit. An unconventional approach, three-dimensional (3-D) integration, attempts to shorten wiring through increased circuit component placement flexibility. The approach considered here for 3-D integration uses wafer-to-wafer aligning and bonding, wafer thinning and deep, high-aspect-ratio Cu via formation. This provides an intimate interconnection between CPU components and an extremely wide path to memory that would be infeasible in conventional or multichip module packaging. This combination of SiGe HBT BiCMOS and 3-D chip stack technologies enables small computing engines in the 16-32-GHz range.