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A new ternary/quaternary content-addressable memory (CAM) architecture using a one-hot-spot block code and two new schemes - for large-scale flow-table lookup has been developed. An NPU-side IP-address compression scheme enables a network processor unit (NPU) to track a CAM and its usage so that IP addresses can be efficiently stored with one-hot-spot block code. A dynamic re-configurable CODEC scheme enables the CAM to store both ternary and quaternary data. With 72-bit data width per word, this CAM, using 0.13-μm stand-alone DRAM technology, can achieve 1.5 million entries, namely, six times more than a conventional static ternary CAM.
Communications, 2005. ICC 2005. 2005 IEEE International Conference on (Volume:2 )
Date of Conference: 16-20 May 2005