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A parallel I/O is integrated on a first-generation CELL processor in 90nm SOI CMOS. A clock-tracking architecture suppresses reference jitter to achieve 6.4Gbit/s/link operation at 21.6mW/Gbit/s. SOI effects on analog circuits, in particular high-speed receivers, are addressed to achieve a receiver sensitivity of ±12mV at 6.4Gbit/s with BER <10-14 measured using 7b PRBS data.
Date of Conference: 10-10 Feb. 2005