Referenced Items are not available for this document.
A parallel I/O is integrated on a first-generation CELL processor in 90nm SOI CMOS. A clock-tracking architecture suppresses reference jitter to achieve 6.4Gbit/s/link operation at 21.6mW/Gbit/s. SOI effects on analog circuits, in particular high-speed receivers, are addressed to achieve a receiver sensitivity of ±12mV at 6.4Gbit/s with BER <10-14 measured using 7b PRBS data.
Published in:
Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International
Date of Conference: 10-10 Feb. 2005
- Page(s):
- 526 - 615 Vol. 1
- ISSN :
- 0193-6530
- Print ISBN:
- 0-7803-8904-2
- INSPEC Accession Number:
- 8652799
- Conference Location :
- San Francisco, CA
- Digital Object Identifier :
- 10.1109/ISSCC.2005.1494101
- Product Type:
- Conference Publications
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