Mixed-voltage I/O buffer with dynamic gate-bias circuit to achieve 3/spl times/V/sub DD/ input tolerance by using 1/spl times/V/sub DD/ devices and single V/sub DD/ supply

This work presents a mixed-voltage I/O buffer realized with 1/spl times/V/sub DD/ devices and single V/sub DD/ power supply to receive 3/spl times/V/sub DD/ input signals without suffering gate-oxide reliability problems. The proposed I/O buffer is verified in a 0.13 /spl mu/m 1V CMOS process. This technique can be extended to receive 4/spl times/V/sub DD/, 5/spl times/V/sub CD/, and even 6/spl times/V/sub DD/ input signals.