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Mixed-voltage I/O buffer with dynamic gate-bias circuit to achieve 3×VDD input tolerance by using 1×VDD devices and single VDD supply

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2 Author(s)
Ming-Dou Ker ; Nat. Chiao-Tung Univ., Hsin-Chu, Taiwan ; Shih-Lun Chen

This work presents a mixed-voltage I/O buffer realized with 1×VDD devices and single VDD power supply to receive 3×VDD input signals without suffering gate-oxide reliability problems. The proposed I/O buffer is verified in a 0.13 μm 1V CMOS process. This technique can be extended to receive 4×VDD, 5×VCD, and even 6×VDD input signals.

Published in:

Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International

Date of Conference:

10-10 Feb. 2005