Referenced Items are not available for this document.
The 24MB level-3 cache on a dual-core Itanium® processor has more than 1.47G transistors. The cache uses an asynchronous design to reduce latency and power, and it includes other power saving and reliability improvement features. The 5-cycle array operates above 2GHz at 0.8V and 85°C while consuming less than 4.2W.
Published in:
Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International
Date of Conference: 10-10 Feb. 2005
- Page(s):
- 488 - 612 Vol. 1
- ISSN :
- 0193-6530
- Print ISBN:
- 0-7803-8904-2
- INSPEC Accession Number:
- 8652782
- Conference Location :
- San Francisco, CA
- Digital Object Identifier :
- 10.1109/ISSCC.2005.1494082
- Product Type:
- Conference Publications
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