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The 24MB level-3 cache on a dual-core Itanium® processor has more than 1.47G transistors. The cache uses an asynchronous design to reduce latency and power, and it includes other power saving and reliability improvement features. The 5-cycle array operates above 2GHz at 0.8V and 85°C while consuming less than 4.2W.
Date of Conference: 10-10 Feb. 2005