Referenced Items are not available for this document.
A read-static-noise-margin-free SRAM cell consists of seven transistors, several of which are low-V, NMOS transistors used to achieve both low-Vdd and high-speed operation. A 64 kb SRAM macro is fabricated in 90 nm CMOS technology. Both a minimum Vdd of 440 mV and a 20 ns access time with a 0.5 V supply are obtained.
Published in:
Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International
Date of Conference: 10-10 Feb. 2005
- Page(s):
- 478 - 611 Vol. 1
- ISSN :
- 0193-6530
- Print ISBN:
- 0-7803-8904-2
- INSPEC Accession Number:
- 8652777
- Conference Location :
- San Francisco, CA
- Digital Object Identifier :
- 10.1109/ISSCC.2005.1494077
- Product Type:
- Conference Publications
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