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A read-static-noise-margin-free SRAM cell for low-Vdd and high-speed applications

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7 Author(s)
Takeda, K. ; NEC Corp., Sagamihara, Japan ; Hagihara, Y. ; Aimoto, Y. ; Nomura, M.
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A read-static-noise-margin-free SRAM cell consists of seven transistors, several of which are low-V, NMOS transistors used to achieve both low-Vdd and high-speed operation. A 64 kb SRAM macro is fabricated in 90 nm CMOS technology. Both a minimum Vdd of 440 mV and a 20 ns access time with a 0.5 V supply are obtained.

Published in:

Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International

Date of Conference:

10-10 Feb. 2005

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