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A 256MB synchronous-burst DDR SRAM with hierarchical bit-line architecture for mobile applications

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11 Author(s)
Suh, Y.H. ; Samsung, Hwasung, South Korea ; Nam, H.Y. ; Kang, S.B. ; Choi, B.G.
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RZ current switches are added to a current steering DAC for high-frequency wideband applications to achieve 800MHz bandwidth at 1st and 2nd Nyquist band without the need for a reverse sinc equalization filter. Implemented in a GaAs HBT process with 4.5 μm2 minimum emitter area, the DAC dissipates 1.2W at -5V with a 1.6GHz clock and 0dBm typical output power.

Published in:

Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International

Date of Conference:

10-10 Feb. 2005