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A 3-GHz 70MB SRAM in 65nm CMOS technology with integrated column-based dynamic power supply

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9 Author(s)
Zhang, K. ; Intel Corp., Hillsboro, OR, USA ; Bhattacharya, U. ; Chen, Z. ; Hamzaoglu, F.
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A 70MB SRAM chip is designed and fabricated in 65nm CMOS technology. A column-based dynamic multi-V, scheme is integrated into the design to improve cell read and write margins while reducing power consumption. The design operates at 3GHz with a 1.1V power supply.

Published in:

Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International

Date of Conference:

10-10 Feb. 2005

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