Referenced Items are not available for this document.
A multiphase PLL, implemented in 90nm SOI CMOS, covers a frequency range from 4.3 to 7.4GHz at a supply voltage of 1V. The ring oscillator-based PLL shows an in-band phase noise of up to -113dBc/Hz at 1 MHz offset and a supply noise rejection of 0.23%delay/%supply due to the rigorous application of CML-type circuit topologies combined with replica biasing.
Published in:
Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International
Date of Conference: 10-10 Feb. 2005
- Page(s):
- 414 - 415 Vol. 1
- ISSN :
- 0193-6530
- Print ISBN:
- 0-7803-8904-2
- INSPEC Accession Number:
- 8652749
- Conference Location :
- San Francisco, CA
- Digital Object Identifier :
- 10.1109/ISSCC.2005.1494045
- Product Type:
- Conference Publications
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