Cart (Loading....) | Create Account
Close category search window

A 70GHz cascaded multi-stage distributed amplifier in 90nm CMOS technology

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Ming-Da Tsai ; Nat. Taiwan Univ., Taipei, Taiwan ; Huei Wang ; Jui-Feng Kuan ; Chih-Sheng Chang

An offset-compensation method uses a peak detector and multiple tap feedback to achieve 1000× improvement in settling time compared to prior art. Measurement results for a 3.125 Gbit/s limit amplifier with 42dB gain implemented in a 0.18 μm CMOS process are presented.

Published in:

Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International

Date of Conference:

10-10 Feb. 2005

Need Help?

IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.