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A 70GHz cascaded multi-stage distributed amplifier in 90nm CMOS technology

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4 Author(s)
Ming-Da Tsai ; Nat. Taiwan Univ., Taipei, Taiwan ; Huei Wang ; Jui-Feng Kuan ; Chih-Sheng Chang

An offset-compensation method uses a peak detector and multiple tap feedback to achieve 1000× improvement in settling time compared to prior art. Measurement results for a 3.125 Gbit/s limit amplifier with 42dB gain implemented in a 0.18 μm CMOS process are presented.

Published in:

Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International

Date of Conference:

10-10 Feb. 2005