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The multi-threaded, parity-protected 128-word register files on a dual-core Itanium®-family processor

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3 Author(s)
E. S. Fetzer ; Intel, Fort Collins, CO, USA ; Lei Wang ; J. Jones

The dual-thread 18-port 128w×82b FPU register file, and the 22-port 128w×65b integer register file of the microprocessor is described. Parity embedded into each register provides soft error detection. The design integrates a charge-compensated thread switch and power-saving features to operate at 1.1V consuming 400mW at maximum frequency.

Published in:

ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005.

Date of Conference:

10-10 Feb. 2005