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A 10Gb/s CMOS adaptive equalizer for backplane applications

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4 Author(s)
Gondi, S. ; California Univ., Los Angeles, CA, USA ; Jri Lee ; Takeuchi, D. ; Razavi, B.

An equalizer employs reverse scaling and dual-loop adaptation to achieve a binary data rate of 10 Gbit/s. Realized in 0.13 μm CMOS technology, the circuit adapts to traces up to 30 inches on FR4 boards while consuming 25 mW from a 1.2 V supply.

Published in:

Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International

Date of Conference:

10-10 Feb. 2005