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A 30mW 8b 200MS/s pipelined CMOS ADC using a switched-opamp technique

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3 Author(s)
Hwi-Cheol Kim ; Seoul Nat. Univ., South Korea ; Deog-Kyoon Jeong ; Kim, Wonchan

An 8b 200MS/s 2.8b-per-stage pipelined ADC is realized in a 0.18μm CMOS process. By using partially switched operational amplifiers, the ADC consumes 30mW from a 1.8V supply and occupies 0.15mm2. The ADC achieves 47.3dB SNDR, 55.8dB SFDR, and 7.6 ENOB for a 90MHz input at 200MS/s.

Published in:

Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International

Date of Conference:

10-10 Feb. 2005

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