A 30mW 8b 200MS/s pipelined CMOS ADC using a switched-opamp technique

An 8b 200MS/s 2.8b-per-stage pipelined ADC is realized in a 0.18/spl mu/m CMOS process. By using partially switched operational amplifiers, the ADC consumes 30mW from a 1.8V supply and occupies 0.15mm/sup 2/. The ADC achieves 47.3dB SNDR, 55.8dB SFDR, and 7.6 ENOB for a 90MHz input at 200MS/s.