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A 10b pipelined ADC has been realized in a digital 90 nm CMOS technology using techniques such as switched opamps and switched-input buffers. Measurements show that this ADC samples at 12 MS/s achieving a peak SNDR of 52.6 dB using a 1.2 V supply. It consumes 3.3 mW and occupies 0.3 mm2 core area.
Date of Conference: 10-10 Feb. 2005