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Enhanced write performance of a 64 Mb phase-change random access memory

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13 Author(s)
Hyung-rok On ; Samsung Electron., Hwasung, South Korea ; Beak-hyung Cho ; Woo Yeong Cho ; Sangbeom Kang
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A 1.8 V 64 Mb phase-change RAM with improved write performance is fabricated in a 0.12 μm CMOS technology. The improvement of RESET and SET distributions is based on cell current regulation and multiple step-down pulse generators. The read access time and SET-write time are 68 ns and 180 ns respectively.

Published in:

ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005.

Date of Conference:

10-10 Feb. 2005