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A 146 mm2 8 Gb NAND flash memory with 70 nm CMOS technology

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25 Author(s)

A 146 mm2 8 Gb NANO flash memory with 4-level programmed cells is fabricated in a 70 nm CMOS technology. A single-sided pad architecture and extended block-addressing scheme without redundancy is adopted for die size reduction. The programming throughput is 6 MB/s and is comparable to binary flash memories.

Published in:

Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International

Date of Conference:

10-10 Feb. 2005