How much mismatch should be simulated in the high density SRAM sense amplifier design

Formats	Non-Member	Member
PDF	$31	$13

Formats

Non-Member

Member

PDF

$31

$13

First Page of the Article

Published in:
Reliability Physics Symposium, 2005. Proceedings. 43rd Annual. 2005 IEEE International

Date of Conference: April 17-21, 2005

Page(s):: 672 - 673
Print ISBN:: 0-7803-8803-8

Digital Object Identifier :: 10.1109/RELPHY.2005.1493198
Product Type:: Conference Publications

Author(s)

Tao Peng
New England Design Center, Cypress Semicond. Corp, Nashua, NH, USA

INSPEC: CONTROLLED INDEXING

SRAM chips

amplifiers

circuit simulation

delays

integrated circuit design

integrated circuit yield

semiconductor device models

statistical analysis

INSPEC: NON CONTROLLED INDEXING

circuit architecture

high density SRAM sense amplifier design

memory density

mismatch delay sensitivity

speed yield

static RAM

statistical model

IEEE TERMS

Circuit simulation

Delay

Doping

MOS devices

MOSFET circuits

Probability

Random access memory

Semiconductor optical amplifiers

Semiconductor process modeling

Threshold voltage

Referenced Items are not available for this document.

No versions found for this document.

Standards Dictionary Terms are available to subscribers only.

Please enter a valid username or password.

For Institutional Users:

More Search Options

How much mismatch should be simulated in the high density SRAM sense amplifier design

Author(s)

INSPEC: CONTROLLED INDEXING

INSPEC: NON CONTROLLED INDEXING

IEEE TERMS

IEEE Account

Purchase Details

Profile Information

Need Help?

Please enter a valid username or password.

For Institutional Users:

More Search Options

How much mismatch should be simulated in the high density SRAM sense amplifier design

Sign In

Author(s)

INSPEC: CONTROLLED INDEXING

INSPEC: NON CONTROLLED INDEXING

IEEE TERMS

IEEE Account

Purchase Details

Profile Information

Need Help?