In this paper, we present the detailed fabrication process, high-frequency characterization, and modeling of through-wafer copper-filled vias ranging from 50- to 70-$mu$m-in diameter on 400-$mu$m-thick silicon substrates. The high aspect ratio via-holes were fabricated by carefully optimizing the inductively coupled plasma deep reactive ion etching process. The high aspect ratio via-holes are completely filled with copper using a bottom-up electroplating approach. The fabricated vias were characterized using different resonating structures based on which the inductance and resistance of the filled via-holes are extracted. For a single 70-$mu$m via, the inductance and resistance are measured to be 254 pH and 0.1$Omega$, respectively. In addition, the effect of the physical arrangement and distribution in multiple-via configurations on the resulting inductance is also evaluated with double straightly aligned quadruple and diagonally aligned quadruple vias. Physical mechanisms of the dependence was depicted by electromagnetic simulation. An equivalent-circuit model is proposed and model parameters are extracted to provide good agreement.