Skip to Main Content
A robust and rapid development procedure for a novel three-dimensional stacking wafer level chip-scaled packaging (3DS-WLCSP), emphasizing the finite-element parametric analysis and experimental validation, is disclosed herein. This design procedure is comprised of the fundamental validation of conventional wafer-level chip-scaled packaging (WLCSP), design methodology development of the test vehicles and then the fabrication of the proposed 3DS-WLCSP structure. Based on the validation of the conventional WLCSP measurement and experiment, a reliable finite-element model can be achieved. However, in order to reduce the product design period, a simplified Glass-WLCSP is chosen as the test vehicle in the parametric design/validation procedure. Through the parametric analysis, one can obtain robust design parameters. Therefore, the proposed 3DS-WLCSP can be fabricated within the validated design parameters.