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Architectural Implications and Process Development of 3-D VLSI Z -Axis Interconnects Using Through Silicon Vias

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6 Author(s)
L. W. Schaper ; High Density Electron. Center, Univ. of Arkansas, Fayetteville, AR, USA ; S. L. Burkett ; S. Spiesshoefer ; G. V. Vangara
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A through-silicon via (TSV) process provides a means of implementing complex, multichip systems entirely in silicon, with a physical packing density many times greater than today's advanced multichip modules. This technology overcomes the resistance–capacitance (RC) delays associated with long, in-plane interconnects by bringing out-of-plane logic blocks much closer electrically, and provides a connection density that makes using those blocks for random logic possible by even small system partitions. TSVs and three dimensional (3-D) stacking technology have the potential to reduce significantly the average wire length of block-to-block interconnects by stacking logic blocks vertically instead of spreading them out horizontally. Although TSVs have great potential, there are many fabrication obstacles that must be overcome. This paper discusses the architectural possibilities enabled by TSVs, and the necessary TSV dimensions for dense Z -axis interconnect among logic blocks. It then describes the TSV requirements for the Defense Advanced Research Projects Agency (DARPA)-funded Vertically Integrated Sensor Arrays (VISA) program, and how those requirements differ from a more general purpose TSV technology. Finally, the TSV fabrication process being implemented at the University of Arkansas (UA) is described in detail. Though this process is being developed for the VISA program, it embodies many of the characteristics of a widely applicable TSV technology.

Published in:

IEEE Transactions on Advanced Packaging  (Volume:28 ,  Issue: 3 )