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Low power JPEG-2000 image compression for industrial embedded applications

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2 Author(s)
Aouadi, I. ; ENSTA, Paris, France ; Hammami, O.

In this paper we described an implementation for a dual JPEG-2000 entropy coder on FPGA and its integration within a JPEG-2000 software encoder on an industrial platform. The use of FPGA as coprocessor on an industrial platform dramatically improves the performance of the JPEG-2000 encoder especially the entropy coding phase. Implementation on a Xilinx XCV405E allows up to 2 parallel coders because of the important use of the BRAMs.

Published in:

Industrial Technology, 2004. IEEE ICIT '04. 2004 IEEE International Conference on  (Volume:3 )

Date of Conference:

8-10 Dec. 2004