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A constraint length and throughput reconfigurable architecture for Viterbi decoders

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3 Author(s)
A. M. Obeid ; Inst. of Microelectronic Syst., Darmstadt Univ. of Technol., Germany ; A. G. Ortiz ; M. Glesner

The use of dynamically reconfigurable architectures is particularly profitable when utilized in multi-standard systems. In this work, we propose a constraint length and throughput reconfigurable architecture for Viterbi decoders. Based on the Radix-2 single delay feedback architecture, we introduce an extension that can realize both the ACS and the trellis window unit of Viterbi decoders. The presented approach facilitates not only constraint length and throughput reconfigurability, but moreover, tradeoff between power consumption and decode quality. The proposed architecture can be easily reconfigured by adding or removing standard building blocks. Moreover, the techniques introduced here can be easily employed in any DSP application with a butterfly-like data flowgraph and therefore, can benefit the design of DSP coarse grain reconfigurable systems.

Published in:

Industrial Technology, 2004. IEEE ICIT '04. 2004 IEEE International Conference on  (Volume:3 )

Date of Conference:

8-10 Dec. 2004