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Design complexity has been increasing exponentially this last decade. In order to cope with such an increase and to keep up designers productivity, higher level specifications were required. Moreover, new synthesis systems, starting with a high level specification, have been developed in order to automate and speed up electronic design. Existing techniques in high-level synthesis mostly assume a simple controller architecture model in the form of a single FSM. However, in reality more complex controller architectures are often used. On the other hand, in the case of programmable processors, the controller architecture is largely defined by the available control-flow instructions in the instruction set. With the wider acceptance of behavioral synthesis, the application of these methods for the design of programmable controllers is of fundamental importance in embedded system technology. This paper describes an important extension of an existing architectural synthesis system targeting the generation of ASIP reprogrammable architectures. The designer can then generate both style of architecture, hardwired and programmable, using the same synthesis system and can quickly evaluate the trade-offs of hardware decisions.