By Topic

The Design of a Hardware Accelerator for Real-Time Complete Visibility Graph Construction and Efficient FPGA Implementation

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)

A valuable geometric structure in mobile robot path planning is the complete visibility graph. This letter proposes new parallel algorithms that can be mapped to reconfigurable hardware for construction of the complete visibility graph in an environment with: 1) multiple convex polygonal objects and 2) multiple nonconvex polygonal objects. Results of implementation in a Xilinx Virtex field-programmable gate array demonstrate that the proposed approach is area–time efficient: the design for an environment with roughly 60 vertices fits on one XCV3200E device and operates at close to 60 MHz.

Published in:

Industrial Electronics, IEEE Transactions on  (Volume:52 ,  Issue: 4 )